1. Field of Invention
This invention relates generally to PMOS semiconductor memories and specifically to adjusting well potential levels in response to changes in output voltage levels.
2. Description of Related Art
FIG. 1 shows a, PMOS negative charge pump 10 having four diode-capacitor stages each including an MOS capacitor C and a diode-connected PMOS transistor D. The diode-connected transistors have a threshold voltage VT equal to, for instance, 0.7 volts. Odd numbered stages are driven by a clock signal CLK. Even numbered stages are driven by the complementary clock signal CLK. Clock signals CLK and CLK swing between ground potential and a positive voltage V.sub.CLK equal to, for instance, a supply voltage V.sub.DD of about 3 volts.
The negative charge pump 10 is typically formed in one or more n- well regions of a p- substrate. FIG. 2 shows the negative charge pump 10 formed in a single n- well region 11 of a p- substrate 12. The p+ diffusion regions 13-18 serve as the source/drain regions of the PMOS diode-connected transistors D.sub.0 -D.sub.4, where the p+ source region 13 of the first diode D.sub.0 is coupled to ground potential and the p+ drain region 18 of the last diode D.sub.4 is coupled to the output terminal OUT of the negative charge pump 10. A p+ diffusion region 19 serves as the p+ contact for the n- well region 11 and is coupled to a welltap terminal WT.
During operation of the negative charge pump 10, the p- substrate 12 is grounded and the n- well region 11 is held at the supply voltage V.sub.DD, thereby preventing the p/n junction therebetween from forward biasing. Initially, the clock signal CLK is low (at ground potential) and its complement signal CLK is high (at V.sub.DD). The threshold voltage V.sub.T of the first stage diode Do forces associated node N.sub.1 to one diode-drop .vertline.V.sub.T.vertline. above ground potential, i.e., to about 0.7 volts. The first capacitor C.sub.1 is thus charged to about 3 volts with respect to ground potential. On the next clock cycle, clock signal CLK transitions low to ground potential and pushes node N.sub.1 to a voltage equal to .vertline.V.sub.T.vertline.-V.sub.CLK =0.7-3=-2.3 volts. The second stage node N.sub.2 is driven to one diode drop above node N.sub.1, i.e., to about -1.6 volts (ideally). Since the clock signal CLK is at V.sub.CLK =3 volts, there is about a -4.6 volt drop across the capacitor C.sub.2 (ideally). On the following clock cycle, clock signal CLK transitions to ground potential and pushes node N.sub.2 from -1.6 volts to -3 volts (ideally). Operation continues as described above, until node N.sub.4, and thus the output terminal OUT, are driven to a high negative voltage. Note that the output terminal OUT (i.e., p+ region 18) is a diode drop .vertline.V.sub.T.vertline. more positive than is node N4 (i.e., p+ region 17).
In some applications, such as when providing erase voltages to a PMOS floating gate memory cell of the type disclosed in U.S. Pat. No. 5,687,118, a negative potential of -11 volts or more is required. The maximum negative voltage of the output terminal OUT is given by: EQU V.sub.OUT (MAX)=V.sub.BD -V.sub.DD -V.sub.T
where, V.sub.BD is the breakdown voltage of the p+ region 17/n- well region 11 junction and V.sub.T is the threshold voltage of PMOS diode D.sub.4. Since the breakdown voltage V.sub.BD is typically about -11 volts, and assuming V.sub.DD =3 volts and V.sub.T =-1 volts, the output terminal OUT of the pump 10 is limited to about -8 volts.
In addition, as the voltage differential between the p+region 17 and the n- well region 11 increases, so does the threshold voltage V.sub.T of the PMOS diode-connected transistors D of the negative charge pump 10. Since the threshold voltage V.sub.T limits the amount by which each stage of the negative charge pump 10 may pull down its output voltage, efficiency of the negative charge pump 10 is also compromised by the increase in V.sub.T (in the negative direction) due to a higher back bias between each of the p+ regions 14-18 and the n- well region 11.